1. Field of the Invention
The present invention relates, in general, to integrated circuit design and, more specifically, integration of test structures into circuit designs and verification of the resulting design.
2. Description of Related Art
As integrated circuits continue to become increasingly more complex, it is becoming increasingly more important to embed into the circuits test structures or objects which can be used during and after manufacture to test the circuit and its various sub-circuits and components. The generation, integration and verification of these test structures is complex and tedious because a circuit may require many specialized test structures and may include embedded circuit blocks which also require test structures. By way of example, FIG. 1 illustrates a relatively simple test ready circuit 10 having a variety of embedded test structures. The circuit includes an embedded circuit block 12 which has logic 14, a dynamic random access memory (DRAM) 16, and a legacy core 18. The test structures which are embedded in embedded block 12 include a logic test controller 20 associated with logic 14, a memory test controller 22 associated with DRAM 16 and a core socket 24 which provides isolation and access to legacy core 18. Top module 30 of circuit 10 includes logic 32, two memory units, including a static Random access memory (SRAM) 34 and read only memory (ROM) 36, a phase locked loop (PLL) 38, an analog-to-digital converter (ADC) 40 and a number of circuit input and output pins. The test structures which were added to the top module include a logic test controller 42 associated with logic 32, a memory test controller 44 associated with SRAM 34 and ROM 36, a phase locked loop test controller 46 associated with PLL 38, an ADC test controller 48 associated with ADC 40, interconnect test controllers 50, 52, and 54, and a test access port (TAP) 56 connected to the various test controllers. Logic blocks 14 and 32 are comprised of memory elements and combinational gates. Memory elements were converted to scannable memory elements and arranged into scan chains. In general, embedded test controllers generate test vectors and analyze output response of sub-circuits and components. The embedded test structures are used cooperatively for testing sub-blocks, which may be buried deep within an embedded block, from the circuit pins such as the test access port.
Automation tools, available from the patentee, LogicVision, Inc. of San Jose, Calif., may be used to generate and verify the test structures and assemble them into a circuit description of a circuit under development. Generally, each test structure has a specialized set of automation tools which provide several optional features, which or may not be included in a particular circuit, depending on the desires of the designer.
Thus, in addition to the complexity of the circuit itself and of the test structures which must be designed into the circuit, a designer faces the additional complexity of operating various automation tools which must be used to analyze the circuit, create the appropriate test structures, create test vectors and patterns to test the circuit, importantly, verify the test structures to ensure that they operate according to design specifications.
Once all test structures have been embedded in the circuit and the circuit design process is substantially complete, all embedded test structures must be verified again, possibly several times, prior to manufacture of the circuit as well as after manufacture.
The embedded test verification process varies from test structure to test structure, but, in general, the process involves operating test controllers in all of their respective modes of operation, and includes generating test benches and scripts to exercise the test controllers on a circuit simulator.
Dedicated verification tools have been developed in an effort to facilitate the verification process. For example, a logic test controller verification tool is required for logic test controllers, a memory test controller verification tool is required for memory test controllers, etc. As indicated above, it is often necessary to run a verification tool several times to test the various modes of a controller. typically a test controller is verified after it has been generated (created), but before it has been integrated into the circuit. This involves exercising the controller directly from its ports. It is verified again after the controller has been integrated into the circuit. This involves exercising the controller more remotely, i.e. from its ports of the circuit. The controller is verified again after top module test structures, such as a TAP, have been inserted into the circuit. In this case, the controller exercised from the TAP to circuit block ports and from the block ports to the controller ports. Finally, all test controllers must be verified again during a test structure sign-off flow. This verification procedure must be performed for each test controller. In the circuit of FIG. 1, there are at least nine test controllers, the test access port, various scan chains and other test structures which must be verified.
It will be seen, then, that each verification tool must be operated several times during the course of embedding test structures into a circuit and that there may be many verification tools which must be used. Clearly, the test structure verification process is complex.
There is a need for a single, unified verification tool and method for simplifying the verification process in circuits having embedded test structures and that can be used during test structure embedding phase of a circuit design, as well as during the final circuit verification phase of circuit design. There is also a need for a verification tool that will generate a test program that will test all test structures in the circuit prior to and after manufacture.